Advances in integrated circuit (IC) technology have involved the fabrication of multiple layers of interconnects. Interconnects are formed on top of the substrate and connect various functional components of the substrate and other electrical connections to the IC.
Capacitors are incorporated between the interconnect layers in order to maximize the use of the space between the interconnect layers. The capacitors formed between the interconnect layers are preferably of a metal-insulator-metal (MIM) construction, as the conductors of the interconnect layers are metal in construction. MIM capacitors may be used to store a charge in a variety of semiconductor devices, that may be utilized in the IC.
Conventional MIM capacitor structures consume a relatively large percentage of the surface area of a semiconductor wafer or chip because they are typically constructed as a large flat structure formed by a low dielectric constant (k) silicon dioxide or nitride capacitor dielectric layer sandwiched between upper and lower metal electrodes, positioned parallel to the wafer surface. In order to reduce the area of these structures, the prior art has attempted to replace the low k material used for the capacitor dielectric layer with high k materials such as BaTiO3 and SiTiO3. However, such high k materials do not adhere well to the metal electrodes, which are still relatively large, thereby leading to delaminations in the capacitor structures. Hence, the capacitor dielectric in conventional MIM capacitor structures is limited to dielectric materials with high dielectric constants, such as BaTiO3 and SiTiO3.
Accordingly, a MIM capacitor structure is needed that utilizes wafer area more efficiently than conventional MIM capacitor structures and allows the use of capacitor dielectrics with high dielectric constants.